1. Field of the Invention
The present invention relates to a forming method of forming a detection mark on a substrate, and a substrate.
2. Description of the Related Art
Along with micropatterning of devices, the fidelity (pattern accuracy) of a pattern (design pattern) transferred to a substrate tends to decrease. This becomes prominent when a pattern with a two-dimensional shape is transferred to a substrate. To solve this, a technique of constituting, by only patterns of one-dimensional shapes, a pattern to be transferred to a substrate, that is, a so-called 1D layout has been proposed in “M. Smayling, ‘32 nm and below Logic Patterning using Optimized Illumination and Double Patterning’ Proc. SPIE 7244, (2009)”.
In a 1D layout, lines and spaces (L/Ss) shown in FIG. 10A are formed on the entire substrate. The L/Ss are partially cut based on cut patterns shown in FIG. 10B, thereby forming circuit elements (transistors) shown in FIG. 10C. This process is mainly applied to a gate process and metal process, and the process applied to the gate process will be exemplified.
FIGS. 11A to 11G are views for explaining the gate process. Assume that a gate oxide film GO, gate material GM, and hard mask HM are formed in order from the substrate side on a silicon substrate ST. As shown in FIG. 11A, an exposure apparatus optically transfers a mask pattern (L/Ss) onto the silicon substrate ST, forming a resist pattern RP of the mask pattern. Since the maximum numerical aperture (NA) of the current exposure apparatus is 1.35, the L/S resolution limit is 0.25×(193/1.35)=36 nm. However, leading-edge devices require an L/S of 30 nm or less, and an L/S finer than 36 nm needs to be formed in practice. A case in which an L/S of 20 nm/20 nm is formed will be exemplified. More specifically, first, the resist pattern RP is formed at 20 nm/60 nm=L/S larger than the resolution limit of the exposure apparatus. Lithography of such an L/S is more difficult than lithography of 40 nm/40 nm=L/S at which the line and space pitches are equal. Therefore, after forming 40 nm/40 nm=L/S, the resist pattern may be isotropically etched by an oxygen plasma or the like to form 20 nm/60 nm=L/S.
Then, as shown in FIG. 11B, an oxide film OC is formed by spin coating, CVD, sputtering, or the like on the substrate on which the resist pattern RP has been formed. The thickness (film thickness) of the oxide film OC is set to be equal to the line width (20 nm) of an L/S to be formed on the silicon substrate ST. The oxide film OC formed on each side surface of the resist pattern RP is called a side wall. Since the oxide film OC is isotropically formed (deposited), the width of the side wall is equal to the thickness of the oxide film OC formed on the upper surface of the resist pattern RP. In other words, the width of the side wall becomes 20 nm, which is the line width of the L/S to be formed on the silicon substrate ST. Although the oxide film has been exemplified, the purpose of this process is to etch an underlying film, and the target film may be another film such as a carbon film.
After that, as shown in FIG. 11C, the oxide film OC is anisotropically etched until the surface of the resist pattern RP appears. As shown in FIG. 11D, the resist pattern RP is removed by an oxygen plasma. As a result, 20-nm L/Ss are formed by the side walls.
Thereafter, as shown in FIG. 11E, the hard mask HM is etched using the side walls as a mask. The gate material GM is etched using the pattern of the hard mask HM, as shown in FIG. 11F, and the hard mask HM is removed, as shown in FIG. 11G. Accordingly, L/Ss of 20 nm/20 nm are formed.
The exposure apparatus transfers, to a substrate, even a mark used for alignment or a mark used for overlay inspection after transferring a pattern. To align a pattern formed on a substrate and the pattern of a mask, the exposure apparatus detects an alignment mark formed on the substrate, and acquires the position (position information) of the pattern formed on the substrate. As a detection system which detects an alignment mark, an optical detection system which optically detects an alignment mark is employed in the arrangement of the exposure apparatus. Although the shape of the alignment mark is decided based on the specifications of the exposure apparatus, it is much larger than a device pattern so that the alignment mark can be optically detected. In many cases, in the detection system, bright field is used.
In overlay inspection, the second overlay mark (resist pattern) is formed in the overlay process on the first overlay mark formed in a preceding process, and the overlay state is inspected. Even in overlay inspection, an optical detection system is adopted in terms of processing ability, and bright field is used in many cases. As the overlay mark, a type in which a square second overlay mark OM2 is overlaid on a square first overlay mark OM1, as shown in FIG. 12A, has been used conventionally. Recently, a type in which the first overlay mark OM1 and second overlay mark OM2 are constituted by sets of small rectangles, as shown in FIG. 12B, has been proposed in “A. Ueno, ‘Novel at Design Rule Via to Metal Overlay metrology for 193 nm lithography’ IEEE Transactions on semiconductor manufacturing, Vol. 17, No. 3, August 2004”.
To form an L/S finer than 36 nm, a side wall process of forming a side wall is necessary, as described above. FIG. 13A is a plan view showing resist patterns RP and side walls SW formed in a device pattern region PP and a mark region MP of an alignment mark or overlay mark. FIG. 13B is a sectional view showing the device pattern region PP. As described above, if the resist pattern RP is removed, only the side walls SW remain in the device pattern region PP and mark region MP, as shown in FIG. 14. Referring to FIG. 14, a mark such as an alignment mark or overlay mark formed in the mark region MP has a large shape, but only its periphery is constituted by the side wall SW, so the width becomes smaller than 36 nm. In this state, the mark cannot be detected optically.
To solve this, there is proposed a technique of, before forming a device, forming a mark on a silicon substrate by etching, and using this mark as an alignment mark or overlay mark in subsequent processes, as shown in FIG. 15.
However, when a mark formed on a silicon substrate is used, the mark formed on the silicon substrate intervenes in overlay inspection for two processes (that is, a mark formed in each process and the mark formed on the silicon substrate are compared). This is called indirect alignment. Along with micropatterning of recent devices, marks need to be directly aligned in an important process, and the accuracy is poor in indirect alignment. In addition, a device is constituted by many layers, and it becomes difficult to detect a mark formed on a silicon substrate in later processes.